Programmable logic devices ("PLDs") are integrated circuits that may be used to provide logical commands and logical functions in electronic systems. A PLD will typically include a set of input pins, an AND array of logic gates followed by an OR array of logic gates and a set of output pins. A PLD may also provide programmable options, often called macrocells, for one or more feedback lines following the OR array to provide registered output signals and sequential logic capabilities in addition to the combinatorial logic functions provided by the AND/OR arrays alone. Presently, several basic types of PLD architectures are available. In a programmable logic element ("PLE", also referred to as a PROM), the AND array is fixed and the OR array is programmable; PLEs are useful in applications requiring use of most or all of the possible input combinations, such as look-up tables and character generators. However, because the array size must be doubled for each new input that is added to the system, PLEs are limited by cost and performance constraints to a small number of input terminals.
A programmable array logic device ("PAL") has a programmable AND array but a fixed OR array. The PAL device allows formation of arbitrary product or input terms but has fixed output combinations that flow to and through the OR array. A variation of the PAL device is the HAL device, which provides hard array logic that is mask programmed, generally after the design is thoroughly debugged using a corresponding PAL device.
A programmable logic array ("PLA") allows both the AND array and the OR array to be programmed. The PLA device offers the most flexibility among these three classes of devices, but a PLE device or a PAL device is faster than the corresponding PLA device because a dedicated or non-programmable AND gate or OR gate is faster than a programmable AND gate or OR gate, respectively. Applications that do not require a high degree of functional flexibility often use PAL devices to take advantage of the speed available vis-a-vis the corresponding PLA device.
One of the early PAL devices that has attained widespread use is the programmable array logic circuit disclosed by Birkner et al. in U.S. Pat. No. 4,124,899, which disclosed use of twenty input pins and provision of registered output signals with feedback from the OR array output terminals to the AND gate array input terminals. An OR gate output terminal could be disabled so that the corresponding output pin could serve as an input pin with corresponding feedback path to the AND gate array. In a subsequently introduced series of megaPALs, Monolithic Memories increased the size of the AND gate array and allowed a fixed number of AND product terms to be shared between two output terminals.
The Altera EP1200 chip is segmented into a sequence of sub-PALs having only four output terminals, with the output terminals of particular sub-PAL being available as input terminals for some of the other subPALs. All of the input signals are available to all of the AND gates simultaneously, resulting in AND arrays with 64 input terminals, most of which are unused for a given product term.
In U.S. Pat. No. 4,207,556, Sugiyama et al. disclose a programmable logic array having a plurality of logic cell units, each cell comprising a plurality of resistors, diodes and transistors, a wiring matrix of row and column lines, and a switch array unit having a group of switching elements for selectively interconnecting the various row and column lines and the electronic elements. This arrangement sacrifices some density and speed to attain greater functional flexibility by including a large number of electronic elements with variable wiring in each unit.
Ikawa et al. in "A One Day Chip: An Innovative IC Construction Approach . . . " IEEE Journal of Solid State Physics, vol. SC-21, April 1986, pp. 223-227, discloses a VLSI chip that contains 50-200 standard functional blocks of SSI/MSI integration that perform various functions such as inverters, NOR and NAND gates, flip-flops, shift registers, counters, multipliers, etc. Each of these functional units may be connected to other functional units by means of an EEPROM switch matrix. The switch matrix provides flexibility and can easily be reprogrammed, but use of a large number of standard functional blocks may be necessary to provide true flexibility; and most of these blocks would be unused for a given chip function.
Takata et al., in U.S. Pat. No. 4,763,020, disclose a programmable logic device that includes a plurality of connection lines, each connected to an input terminal at one end and to one of a plurality of input buffer circuits at the other end. Each input buffer circuit has an inverting input line and a non-inverting input line extending vertically and has product term lines extending horizontally to a respective sense amplifier. Taken together, the input lines, product term lines and sense amplifiers form a programmable AND plane. Each cross-over point between a product term and an input line is connected by a programmable element. The sense amplifiers are arranged in groups, and the output terminals of the sense amps in each group are connected to input terminals of an associated OR gate. The OR plane is non-programmable as disclosed; Takata et al. indicates that the OR plane may also be programmable, but the technique is not disclosed. An OR gate has its output terminal connected to a D input terminal of a flip-flop, which has an output terminal connected to the device output terminal. Another output terminal of the flip-flop is connected to a feedback circuit that is connected to a pair of input lines in the AND plane through an input buffer circuit. A second OR gate has its output terminal connected to an input terminal of a function cell, and Takata et al. indicate that more than two functional cells may be provided. The output terminals of the functional cells are connected to feedback circuits that are connected to input line pairs in the AND plane through input buffer circuits. The device disclosed by Takata et al. can be structured, for example, as an up-counter a down-counter or a shift register, among other uses.
The devices discussed above provide some functional flexibility when dealing with the normal product terms and sums thereof that are produced by an AND gate/OR gate array but do not provide other functional terms that are used in processing signals such as the product of two n-bit numbers or majority logic.
An object of the invention is to provide a programmable logic device that allows formation of other useful logical variables and functions that are not available in the present technology.